1. Field of the Invention
The present invention relates to an output circuit for driving a load connected thereto.
An output circuit is placed at an output stage of a circuit, such as a memory integrated circuit (IC), and propagates a signal input therefrom out to a load connected to the output circuit. Therefore, a high-speed output circuit with little power consumption and high reliability is in great demand.
2. Description of the Related Art
FIG. 1 is a block diagram of a memory IC with a conventional output circuit.
An address latch la latches an incoming memory address signal to address and read one of a plurality of memory cells constituting a memory cell array 2a. An output data latch 3a latches data read from the cell addressed. An output circuit 4a, which is an output buffer (or buffer amplifier) of low driving ability i.e., high impedance, outputs the data latched in the output data latch 3a to (i.e., drive) a load connected thereto.
The output circuit 4a may be an output buffer of high driving ability i.e., high impedance. However, an output buffer of high driving ability draws a large current to drive the load fast and, therefore, consumes large amounts of power and is subject to a damage from a "bus fight" (i.e., a "bus conflict"). A bus fight is a phenomenon where two signals from output circuits collide and temporarily interfere with each other on a data bus.
For the above reasons, an output buffer of low driving ability is usually used as an output circuit to avoid the ill effects of the output buffer of high driving ability.
FIG. 2 is a timing chart illustrating an operation of the output circuit in FIG. 1. The address signal An is latched in the address latch la at the leading edge of the first clock pulse to address data in the memory cell array 2a. Data read from the memory cell addressed is output via the output circuit 4a as an data-out (Dn) signal.
As shown in FIG. 2, the data-out signal is blunt and unsteady at its leading and trailing edges, eventually, making propagation delay time (i.e., memory access time T) long. Hereinafter, the access time T is defined, as shown in FIG. 2, as the period from the leading edge of the next clock pulse until the data-out signal becomes steady. The data-out signal becomes blunt and unsteady at the leading and trailing edges because an output buffer of the low driving ability requires time to charge and discharge stray capacitance associated with, for example, the output buffer.
Thus, the output circuit of the related art, which comprises an output buffer of low driving ability, has an unnecessarily long memory access time T (or propagation delay time) and, therefore decreases processing speeds of a memory device and other logical circuits using such output circuit.